Datasheet

Section 11 16-Bit Timer Pulse Unit (TPU)
Rev. 3.00 Mar 17, 2006 page 593 of 926
REJ09B0283-0300
Status Flag Clearing Timing: After a status flag is read as 1 by the CPU, it is cleared by writing
0 to it. When the DTC or DMAC is activated, the flag is cleared automatically. Figure 11.42
shows the timing for status flag clearing by the CPU, and figure 11.43 shows the timing for status
flag clearing by the DTC or DMAC.
Status flag
Write signal
Address
TSR address
Interrupt
request
signal
TSR write cycle
T1 T2
φ
Figure 11.42 Timing for Status Flag Clearing by CPU
Interrupt
request
signal
Status flag
Address
Source address
DTC/DMAC
read cycle
T1 T2
Destination
address
T1 T2
DTC/DMAC
write cycle
φ
Figure 11.43 Timing for Status Flag Clearing by DTC/DMAC Activation