Datasheet

Section 11 16-Bit Timer Pulse Unit (TPU)
Rev. 3.00 Mar 17, 2006 page 573 of 926
REJ09B0283-0300
• PWM mode 2
PWM output is generated using one TGR as the cycle register and the others as duty cycle
registers. The output specified in TIOR is performed by means of compare matches. Upon
counter clearing by a synchronization register compare match, the output value of each pin is
the initial value set in TIOR. If the set values of the cycle and duty cycle registers are identical,
the output value does not change when a compare match occurs.
In PWM mode 2, a maximum 15-phase PWM output is possible by combined use with
synchronous operation.
The correspondence between PWM output pins and registers is shown in table 11.30.
Table 11.30 PWM Output Registers and Output Pins
Output Pins
Channel Registers PWM Mode 1 PWM Mode 2
0 TGRA_0 TIOCA0 TIOCA0
TGRB_0 TIOCB0
TGRC_0 TIOCC0 TIOCC0
TGRD_0 TIOCD0
1 TGRA_1 TIOCA1 TIOCA1
TGRB_1 TIOCB1
2 TGRA_2 TIOCA2 TIOCA2
TGRB_2 TIOCB2
3 TGRA_3 TIOCA3 TIOCA3
TGRB_3 TIOCB3
TGRC_3 TIOCC3 TIOCC3
TGRD_3 TIOCD3
4 TGRA_4 TIOCA4 TIOCA4
TGRB_4 TIOCB4
5 TGRA_5 TIOCA5 TIOCA5
TGRB_5 TIOCB5
Note: In PWM mode 2, PWM output is not possible for the TGR register in which the cycle is set.