Datasheet

Section 10 I/O Ports
Rev. 3.00 Mar 17, 2006 page 520 of 926
REJ09B0283-0300
• PH1/CS5/RAS5
*
/SDRAMφ
*
The pin function is switched as shown below according to the operating mode, DCTL pin, bit
EXPE, bit CS5E, bits RMTS2 to RMTS0, and bit PH1DDR.
Operating
mode
1, 2, 4, 5, 6 3
*
, 7 —
EXPE — 0 1 —
Area 5 Normal space DRAM space — Normal space DRAM space —
DCTL 0 1
CS5E 0101—0101—
PH1DDR 010101 — 01010101— —
Pin function PH1
input
PH1
output
PH1
input
CS5
output
PH1
input
PH1
output
RAS5
*
output
PH1
input
PH1
output
PH1
input
PH1
output
PH1
input
CS5
output
PH1
input
PH1
output
RAS5
*
output
SDRAM
*
φ output
Note: * Only in H8S/2678R Group.
• PH0/CS4/RAS4
*
/WE
*
The pin function is switched as shown below according to the operating mode, bit EXPE, bit
CS4E, bits RMTS2 to RMTS0, and bit PH0DDR.
Operating
mode
1, 2, 4, 5, 6 3
*
, 7
EXPE — 0 1
Area 4 — Normal space DRAM
space
Syn-
chronous
DRAM
*
space
— — Normal space DRAM
space
Syn-
chronous
DRAM
*
space
SC4E 0 1 — 0 1
PH1DDR0101—— 010101——
Pin function PH0
input
PH0
output
PH0
input
CS4
output
RAS4
*
output
WE
*
output
PH0
input
PH0
output
PH0
input
PH0
output
PH0
input
CS4
output
RAS4
*
output
WE
*
output
Note: * Only in H8S/2678R Group.