Datasheet

Section 10 I/O Ports
Rev. 3.00 Mar 17, 2006 page 517 of 926
REJ09B0283-0300
10.16.1 Port H Data Direction Register (PHDDR)
The individual bits of PHDDR specify input or output for the pins of port H.
PHDDR cannot be read; if it is, an undefined value will be read.
Bit Bit Name Initial Value R/W Description
7
to
4
— All 0 — Reserved
If these bits are read, they will return an undefined
value.
3 PH3DDR 0 W
2 PH2DDR 0 W
1 PH1DDR 0 W
0 PH0DDR 0 W
• Modes 1, 2, 3
*
(when EXPE = 1), 4, 5, 6, and 7
(when EXPE = 1)
When the OE output enable bit (OEE) and OE
output select bit (OES) are set to 1, pin PH3
functions as the OE output pin. Otherwise, when bit
CS7E is set to 1, pin PH3 functions as a CS output
pin when the corresponding PHDDR bit is set to 1,
and as an input port when the bit is cleared to 0.
When bit CS7E is cleared to 0, pin PH3 is an I/O
port, and its function can be switched with PHDDR.
When the CS output enable bits (CS6E to CS4E)
are set to 1, pins PH2 to PH0 function as CS output
pins when the corresponding PHDDR bit is set to 1,
and as I/O ports when the bit is cleared to 0. When
CS6E to CS4E are cleared to 0, pins PH2 to PH0
are I/O ports, and their functions can be switched
with PHDDR.
• Mode 3
*
(EXPE = 0) and Mode 7 (when EXPE =
0)
Pins PH3 to PH0 are I/O ports, and their functions
can be switched with PHDDR.
Note: * Only in H8S/2678R Group.