Datasheet

Section 10 I/O Ports
Rev. 3.00 Mar 17, 2006 page 511 of 926
REJ09B0283-0300
Bit Bit Name Initial Value R/W Description
7— 0 — Reserved
If read, it returns an undefined value.
6 PG6DDR 0 W
5 PG5DDR 0 W
4 PG4DDR 0 W
3 PG3DDR 0 W
2 PG2DDR 0 W
1 PG1DDR 0 W
0 PG0DDR 1/0
*
1
W
• Modes 1, 2, 4, 5, and 6
Pins PG6 to PG4 function as bus control
input/output pins (BREQO, BACK, and BREQ) when
the appropriate bus controller settings are made.
Otherwise, these pins are I/O ports, and their
functions can be switched with PGDDR.
When the CS output enable bits (CS3E to CS0E)
are set to 1, pins PG3 to PG0 function as CS output
pins when the corresponding PGDDR bit is set to 1,
and as input ports when the bit is cleared to 0.
When CS3E to CS0E are cleared to 0, pins PG3 to
PG0 are I/O ports, and their functions can be
switched with PGDDR.
• Modes 3
*
2
, 7 (when EXPE = 1)
Pins PG6 to PG4 function as bus control
input/output pins (BREQO, BACK, and BREQ) when
the appropriate bus controller settings are made.
Otherwise, these pins are output ports when the
corresponding PGDDR bit is set to 1, and as input
ports when the bit is cleared to 0.
When the CS output enable bits (CS3E to CS0E)
are set to 1, pins PG3 to PG0 function as CS output
pins when the corresponding PGDDR bit is set to 1,
and as input ports when the bit is cleared to 0.
When CS3E to CS0E are cleared to 0, pins PG3 to
PG0 are I/O ports, and their functions can be
switched with PGDDR.
• Modes 3
*
2
, 7 (when EXPE = 0)
Pins PG6 to PG0 are I/O ports, and their functions
can be switched with PGDDR.
Notes: 1. PG0DDR is initialized to 1 in modes 1, 2, 5, and 6, and to 0 in modes 3, 4, and 7.
2. Only in H8S/2678R Group.