Datasheet

Section 10 I/O Ports
Rev. 3.00 Mar 17, 2006 page 509 of 926
REJ09B0283-0300
• PF1/UCAS/DQMU
*
2
/IRQ14
The pin function is switched as shown below according to the combination of the operating
mode, bit EXPE, bits RMTS2 to RMTS0 in DRAMCR, and bit PF1DDR.
Operating
mode
1, 2, 4, 5, 3
*
2
, 7
EXPE — 0 1
Areas
2 to 5
Any of
areas
2 to 5
is
DRAM
space
Areas 2 to 5
are all normal
space
— Any of
areas
2 to 5
is
DRAM
space
Areas 2 to 5
are all normal
space
PF1DDR—0101—01
UCAS
output
PF1
input
PF1
output
PF1
input
PF1
output
UCAS
output
PF1
input
PF1
output
Pin function
IRQ14 interrupt
*
1
Notes: 1. IRQ14 interrupt input when bit ITS14 is cleared to 0 in ITSR.
2. Only in H8S/2678R Group.
• PF0/WAIT
The pin function is switched as shown below according to the operating mode, bit EXPE, bit
WAITE in BCR, and bit PF0DDR.
Operating
mode
1, 2, 4, 5, 6 3
*
, 7
EXPE — 0 1
WAITE 0 1 — 0 1
PF0DDR01—0101—
Pin function PF0
input
PF0
output
WAIT
input
PF0
input
PF0
output
PF0
input
PF0
output
WAIT
input
Note: * Only in H8S/2678R Group.