Datasheet

Section 10 I/O Ports
Rev. 3.00 Mar 17, 2006 page 508 of 926
REJ09B0283-0300
• PF3/LWR
The pin function is switched as shown below according to the operating mode, bit EXPE, bit
PF3DDR, and bit LWROE.
Operating
mode
1, 2, 4, 5, 6 3
*
, 7
EXPE — 0 1
LWROD 1 0 — 1 0
PF3DDR—0101—01
Pin function LWR
output
PF3
input
PF3
output
PF3
input
PF3
output
LWR
output
PF3
input
PF3
output
Note: * Only in H8S/2678R Group.
• PF2/LCAS/DQML
*
2
/IRQ15
The pin function is switched as shown below according to the combination of the operating
mode, bit EXPE, bits RMTS2 to RMTS0 in DRAMCR, bits ABW5 to ABW2 in ABWCR, and
bit PF2DDR.
Operating
mode
1, 2, 4, 5, 6 3
*
2
, 7
EXPE — 0 1
Areas
2 to 5
Any
DRAM
space
area is
16-bit
bus
space
All DRAM
space areas
are 8-bit bus
space, or areas
2 to 5 are all
normal space
—Any
DRAM
space
area is
16-bit
bus
space
All DRAM
space areas
are 8-bit bus
space, or areas
2 to 5 are all
normal space
PF2DDR—0101—01
LCAS
output
PF2
input
PF2
output
PF2
input
PF2
output
LCAS
output
PF2
input
PF2
output
Pin function
IRQ15 interrupt input
*
1
Notes: 1. IRQ15 interrupt input when bit ITS15 is cleared to 0 in ITSR.
2. Only in H8S/2678R Group.