Datasheet

Section 10 I/O Ports
Rev. 3.00 Mar 17, 2006 page 504 of 926
REJ09B0283-0300
10.14.1 Port F Data Direction Register (PFDDR)
The individual bits of PFDDR specify input or output for the pins of port F.
PFDDR cannot be read; if it is, an undefined value will be read.
Bit Bit Name Initial Value R/W Description
7 PF7DDR 1/0
*
1
W
6 PF6DDR 0 W
5 PF5DDR 0 W
4 PF4DDR 0 W
3 PF3DDR 0 W
2 PF2DDR 0 W
1 PF1DDR 0 W
0 PF0DDR 0 W
• Modes 1, 2, 4, 5, and 6
Pin PF7 functions as the φ output pin when the
corresponding PFDDR bit is set to 1, and as an
input port when the bit is cleared to 0.
Pin PF6 functions as the AS output pin when ASOE
is set to 1. When ASOE is cleared to 0, pin PF6 is
an I/O port and its function can be switched with
PF6DDR.
Pins PF5 and PF4 are automatically designated as
bus control outputs (RD and HWR).
Pin PF3 functions as the LWR output pin when
LWROE is set to 1. When LWROE is cleared to 0,
pin PF3 is an I/O port and its function can be
switched with PF3DDR.
Pins PF2 and PF1 are designated as I/O ports and
their function can be switched with PFDDR.
Pins PF0 functions as bus control input/output pin
(LCAS, UCAS, and WAIT) when the appropriate bus
controller settings are made. Otherwise, these pins
are output ports when the corresponding PFDDR bit
is set to 1, and input ports when the bit is cleared to
0.
• Modes 3
*
2
and 7 (when EXPE = 1)
Pin PF7 to PF3 function in the same way as in
modes 1, 2, 4, 5, and 6.
Pins PF2 to PF0 function as bus control input/output
pins (LCAS, UCAS, and WAIT) when the
appropriate PFCR2 settings are made. Otherwise,
these pins are I/O ports, and their functions can be
switched with PFDDR.