Datasheet
Section 1 Overview
Rev. 3.00 Mar 17, 2006 page 3 of 926
REJ09B0283-0300
1.2 Block Diagram
PE7/D7
PE6/D6
PE5/D5
PE4/D4
PE3/D3
PE2/D2
PE1/D1
PE0/D0
Internal data bus
Peripheral address bus
Peripheral data bus
PD7/D15
PD6/D14
PD5/D13
PD4/D12
PD3/D11
PD2/D10
PD1/D9
PD0/D8
Port D
PLLVcc
PLLVss
Vcc
Vcc
Vcc
Vcc
Vcc
Vss
Vss
Vss
Vss
Vss
Vss
Vss
PA7/A23
PA6/A22
PA5/A21
PA4/A20
PA3/A19
PA2/A18
PA1/A17
PA0/A16
PB7/A15
PB6/A14
PB5/A13
PB4/A12
PB3 / A11
PB2/A10
PB1/A9
PB0/A8
PC7/A7
PC6/A6
PC5/A5
PC4/A4
PC3/A3
PC2/A2
PC1/A1
PC0/A0
P35/SCK1/(OE)
P34/SCK0
P33/RxD1
P32/RxD0/IrRxD
P31/TxD1
P30/TxD0/IrTxD
P57/AN15/DA3/IRQ7
P56/AN14/DA2/IRQ6
P55/AN13/IRQ5
P54/AN12/IRQ4
P53/ADTRG//IRQ3
P52/SCK2/IRQ2
P51/RxD2/IRQ1
P50/TxD2/IRQ0
P47/AN7/DA1
P46/AN6/DA0
P45/AN5
P44/AN4
P43/AN3
P42/AN2
P41/AN1
P40/AN0
Vref
AVcc
AV
ss
P20/PO0/TIOCA3/(IRQ8)
P21/PO1/TIOCB3/(IRQ9)
P22/PO2/TIOCC3/(IRQ10)
P23/PO3/TIOCD3/(IRQ11)
P24/PO4/TIOCA4/(IRQ12)
P25/PO5/TIOCB4/(IRQ13)
P26/PO6/TIOCA5/EDRAK0/(IRQ14)
P27/PO7/TIOCB5/EDRAK1/(IRQ15)
P10/PO8/TIOCA0
P11/PO9/TIOCB0
P12/PO10/TIOCC0/TCLKA
P13/PO11/TIOCD0/TCLKB
P14/PO12/TIOCA1
P15/PO13/TIOCB1/TCLKC
P16/PO14/TIOCA2/EDRAK2
P17/PO15/TIOCB2/TCLKD/EDRAK3
P65/TMO1/DACK1/IRQ13
P64/TMO0/DACK0/IRQ12
P63/TMCI1/TEND1/IRQ11
P62/TMCI0/TEND0/IRQ10
P61/TMRI1/DREQ1/IRQ9
P60/TMRI0/DREQ0/IRQ8
PG6/BREQ
PG5/BACK
PG4/BREQO
PG3/CS3
PG2/CS2
PG1/CS1
PG0/CS0
PF7/φ
PF6/AS
PF5/RD
PF4/HWR
PF3/LWR
PF2/LCAS/IRQ15
PF1/UCAS/IRQ14
PF0/WAIT
ROM
*
1
(Flash memory
or mask ROM)
RAM
WDT
TPU × 6 channels
TMR × 2 channels
SCI × 3 channels
8-bit D/A converter
10-bit A/D converter
PPG
MD2
MD1
MD0
EXTAL
XTAL
STBY
RES
WDTOVF
FWE
*
2
NMI
H8S/2600 CPU
DTC
Interrupt controller
Port E
Port
4
P75/EDACK1/(DACK1)
P74/EDACK0/(DACK0)
P73/ETEND1/(TEND1)
P72/ETEND0/(TEND0)
P71/EDREQ1/(DREQ1)
P70/EDREQ0/(DREQ0)
Port
7
PH3/CS7/OE/(IRQ7)
PH2/CS6/(IRQ6)
PH1/CS5
PH0/CS4
Port
H
Port
2
Port
1
DMAC
EXDMAC
Internal address bus
P85/EDACK3/(IRQ5)
P84/EDACK2/(IRQ4)
P83/ETEND3/(IRQ3)
P82/ETEND2/(IRQ2)
P81/EDREQ3/(IRQ1)
P80/EDREQ2/(IRQ0)
Port
8
Bus controller
Notes:
Port
6
Port
G
Port
F
Port
A
Port
B
Port
C
Port
3
Port
5
ROM is not supported in the ROMless version.
The FWE pin is used only in the F-ZTAT version. In other versions, this is an NC pin.
1.
2.
PLL
Clock
pulse
generator
Figure 1.1 H8S/2678 Group Internal Block Diagram