Datasheet

Section 1 Overview
Rev. 3.00 Mar 17, 2006 page 1 of 926
REJ09B0283-0300
Section 1 Overview
1.1 Features
• High-speed H8S/2600 central processing unit with an internal 16-bit architecture
Upward-compatible with H8/300 and H8/300H CPUs on an object level
Sixteen 16-bit general registers
69 basic instructions
• Various peripheral functions
DMA controller (DMAC)
EXDMA controller (EXDMAC)
Data transfer controller (DTC)
16-bit timer-pulse unit (TPU)
Programmable pulse generator (PPG)
8-bit timer (TMR)
Watchdog timer (WDT)
Asynchronous or clocked synchronous serial communication interface (SCI)
10-bit A/D converter
8-bit D/A converter
Clock pulse generator
• On-chip memory
ROM Type Model ROM RAM
Flash memory version HD64F2676 256 kbytes 8 kbytes
Masked ROM version HD6432676 256 kbytes 8 kbytes
HD6432675 128 kbytes 8 kbytes
HD6432673 64 kbytes 8 kbytes
ROMless version HD6412674R — 32 kbytes
HD6412670 — 8 kbytes
• General I/O ports
I/O pins: 103
Input-only pins: 12
• Supports various power-down states