Datasheet

Section 10 I/O Ports
Rev. 3.00 Mar 17, 2006 page 471 of 926
REJ09B0283-0300
• P61/TMRI1/DREQ1/IRQ9
The pin function is switched as shown below according to the combination of bit DMACS in
PFCR2, bit P61DDR, and bit ITS9 in ITSR.
P61DDR 0 1
P61 input P61 output
TMRI1 input
*
1
DREQ1 input
*
2
Pin function
IRQ9 interrupt input
*
3
Notes: 1. When used as the counter reset input pin for the TMR, both the CCLR1 and CCLR0 bits
in TCR_1 should be set to 1.
2. DREQ1 input when DMAKS = 0.
3. IRQ9 interrupt input when ITS9 = 0.
• P60/TMRI0/DREQ0/IRQ8
The pin function is switched as shown below according to the combination of bit DMACS in
PFCR2, bit P60DDR, and bit ITS8 in ITSR.
P60DDR 0 1
P60 input P60 output
TMRI0 input
*
1
DREQ0 input
*
2
Pin function
IRQ8 interrupt input
*
3
Notes: 1. When used as the counter reset input pin for the TMR, both the CCLR1 and CCLR0 bits
in TCR_0 should be set to 1.
2. DREQ0 input when DMAKS = 0.
3. IRQ8 interrupt input when ITS8 = 0.