Datasheet

Section 10 I/O Ports
Rev. 3.00 Mar 17, 2006 page 446 of 926
REJ09B0283-0300
TPU channel 5
settings
(2) (1) (2) (2) (1) (2)
MD3 to MD0 B'0000, B'01xx B'0010 B'0011
IOB3 to IOB0 B'0000
B'0100
B'1xxx
B'0001 to B'0011
B'0101 to B'0111
B'xx00 Other than B'xx00
CCLR1, CCLR0 — — — — Other
than
B'10
B'10
Output function — Output compare
output
——PWM
mode 2
output
—
x: Don’t care
• P26/PO6/TIOCA5/IRQ14/EDRAK0
The pin function is switched as shown below according to the combination of the TPU channel
5 settings (by bits MD3 to MD0 in TMDR5, bits IOA3 to IOA0 in TIOR5, and bits CCLR1
and CCLR0 in TCR5), bit NDER6 in NDERL, bit EDRAKE in EDMDR0, bit P26DDR, and
bit ITS14 in ITSR.
Modes 1, 2, 3
*
4
(EXPE = 1), 4, 5, 6, 7 (EXPE = 1)
EDRAKE 0 1
TPU channel 5
settings
(1) in table
below
(2) in table below —
P26DDR — 0 1 1 —
NDER6 — — 0 1 —
P26
input
P26
output
PO6
output
EDRAK0
output
TIOCA5
output
TIOCA input
*
1
Pin function
IRQ14 interrupt input
*
2