Datasheet

Section 10 I/O Ports
Rev. 3.00 Mar 17, 2006 page 440 of 926
REJ09B0283-0300
• P12/PO10/TIOCC0/TCLKA
The pin function is switched as shown below according to the combination of the TPU channel
0 settings (by bits MD3 to MD0 in TMDR0, bits IOC3 to IOC0 in TIOR0L, and bits CCLR2
to CCLR0 in TCR0), bits TPSC2 to TPSC0 in TCR0 to TCR5, bit NDER10 in NDERH, and
bit P12DDR.
TPU channel 0
settings
(1) in table
below
(2) in table below
P12DDR — 0 1 1
NDER10 — — 0 1
P12 input P12 output PO10 outputTIOCC0 output
TIOCC0 input
*
1
Pin function
TCLKA input
*
2
Notes: 1. TIOCC0 input when MD3 to MD0 = B'0000 and IOC3 to IOC0 = B'10xx.
2. TCLKA input when the setting for any of TCR0 to TCR5 is TPSC2 to TPSC0 = B'100.
TCLKA input when phase counting mode is set for channels 1 and 5.
TPU channel 0
settings
(2) (1) (2) (1) (1) (2)
MD3 to MD0 B'0000 B'001x B'0010 B'0011
IOC3 to IOC0 B'0000
B'0100
B'1xxx
B'0001 to B'0011
B'0101 to B'0111
B'xx00 Other
than
B'xx00
Other than B'xx00
CCLR2, CCLR0 — — — — Other
than
B'101
B'101
Output function — Output compare
output
—PWM
*
3
mode 1
output
PWM
mode 2
output
—
x: Don’t care
Note: 3. TIOCD0 output disabled.
Output disabled and settings (2) effective when BFA = 1 or BFB = 1 in TMDR0.