Datasheet

Rev. 3.00 Mar 17, 2006 page xlvii of l
Table 11.28 Register Combinations in Buffer Operation........................................................... 567
Table 11.29 Cascaded Combinations......................................................................................... 570
Table 11.30 PWM Output Registers and Output Pins................................................................ 573
Table 11.31 Clock Input Pins in Phase Counting Mode............................................................. 577
Table 11.32 Up/Down-Count Conditions in Phase Counting Mode 1 ....................................... 578
Table 11.33 Up/Down-Count Conditions in Phase Counting Mode 2 ....................................... 579
Table 11.34 Up/Down-Count Conditions in Phase Counting Mode 3 ....................................... 580
Table 11.35 Up/Down-Count Conditions in Phase Counting Mode 4 ....................................... 581
Table 11.36 TPU Interrupts........................................................................................................ 584
Section 12 Programmable Pulse Generator (PPG)
Table 12.1 Pin Configuration................................................................................................... 607
Section 13 8-Bit Timers (TMR)
Table 13.1 Pin Configuration................................................................................................... 629
Table 13.2 Clock Input to TCNT and Count Condition........................................................... 632
Table 13.3 8-Bit Timer Interrupt Sources ................................................................................ 642
Table 13.4 Timer Output Priorities .......................................................................................... 646
Table 13.5 Switching of Internal Clock and TCNT Operation ................................................ 647
Section 14 Watchdog Timer
Table 14.1 Pin configuration.................................................................................................... 650
Table 14.2 WDT Interrupt Source............................................................................................ 656
Section 15 Serial Communication Interface (SCI, IrDA)
Table 15.1 Pin Configuration................................................................................................... 664
Table 15.2 Relationships between N Setting in BRR and Bit Rate B ...................................... 679
Table 15.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (1)............................. 680
Table 15.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (2)............................. 681
Table 15.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (3)............................. 682
Table 15.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (4)............................. 683
Table 15.4 Maximum Bit Rate for Each Frequency (Asynchronous Mode)............................ 684
Table 15.5 Maximum Bit Rate with External Clock Input (Asynchronous Mode).................. 684
Table 15.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) ...................... 685
Table 15.7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode)...... 686
Table 15.8 Examples of Bit Rate for Various BRR Settings (Smart Card Interface Mode)
(when n = 0 and S = 372)....................................................................................... 687
Table 15.9 Maximum Bit Rate at Various Frequencies (Smart Card Interface Mode)
(when S = 372)....................................................................................................... 687
Table 15.10 Serial Transfer Formats (Asynchronous Mode)..................................................... 692
Table 15.11 SSR Status Flags and Receive Data Handling........................................................ 699