Datasheet

Section 10 I/O Ports
Rev. 3.00 Mar 17, 2006 page 435 of 926
REJ09B0283-0300
TPU channel 2
settings
(2) (1) (2) (2) (1) (2)
MD3 to MD0 B'0000, B'01xx B'0010 B'0011
IOB3 to IOB0 B'0000
B'0100
B'1xxx
B'0001 to B'0011
B'0101 to B'0111
B'xx00 B'xx00 Other than B'xx00
CCLR1, CCLR0 — — — — Other
than
B'10
B'10
Output function — Output compare
output
——PWM
mode 2
output
—
x: Don’t care
• P16/PO14/TIOCA2/EDRAK2
The pin function is switched as shown below according to the combination of the TPU channel
2 settings (by bits MD3 to MD0 in TMDR2, bits IOB3 to IOB0 in TIOR2, and bits CCLR1
and CCLR0 in TCR2), bit NDER14 in NDERH, bit EDRAKE in EDMDR2 and bit P16DDR.
Modes 1, 2, 3
*
3
(EXPE = 1), 4, 5, 6, 7 (EXPE = 1)
EDRAKE 0 1
TPU channel 2
settings
(1) in table
below
(2) in table below —
P16DDR — 0 1 1 —
NDER14 — — 0 1 —
TIOCA2
output
P16
input
P16
output
PO14
output
EDRAK2
output
Pin function
TIOCA input
*
1