Datasheet

Section 10 I/O Ports
Rev. 3.00 Mar 17, 2006 page 427 of 926
REJ09B0283-0300
Section 10 I/O Ports
Table 10.1 summarizes the port functions. The pins of each port also have other functions such as
input/output or external interrupt input pins of on-chip peripheral modules. Each I/O port includes
a data direction register (DDR) that controls input/output, a data register (DR) that stores output
data, and a port register (PORT) used to read the pin states. The input-only ports do not have a DR
or DDR register.
Ports A to E have a built-in pull-up MOS function and a input pull-up MOS control register (PCR)
to control the on/off state of input pull-up MOS.
Ports 3 and A include an open-drain control register (ODR) that controls the on/off state of the
output buffer PMOS.
Ports 1 to 3, 5 (P50 to P53), and 6 to 8 can drive a single TTL load and 30 pF capacitive load.
Ports A to H can drive a single TTL load and 50 pF capacitive load.
All the I/O ports can drive a Darlington transistor when outputting data.
Ports 1 and 2 are Schmitt-triggered inputs. Ports 5, 6, F (PF1, PF2), and H (PH2, PH3) are
Schmitt-triggered inputs when used as the IRQ input.