Datasheet

Section 9 Data Transfer Controller (DTC)
Rev. 3.00 Mar 17, 2006 page 426 of 926
REJ09B0283-0300
9.8 Usage Notes
9.8.1 Module Stop Mode Setting
DTC operation can be disabled or enabled using the module stop control register. The initial
setting is for DTC operation to be enabled. Register access is disabled by setting module stop
mode. Module stop mode cannot be set while the DTC is activated. For details, refer to section 22,
Power-Down Modes.
9.8.2 On-Chip RAM
The MRA, MRB, SAR, DAR, CRA, and CRB registers are all located in on-chip RAM. When the
DTC is used, the RAME bit in SYSCR must not be cleared to 0.
9.8.3 DTCE Bit Setting
For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR. If all interrupts
are disabled, multiple activation sources can be set at one time (only at the initial setting) by
writing data after executing a dummy read on the relevant register.
• DMAC Transfer End Interrupt
When DTC transfer is activated by a DMAC transfer end interrupt, regardless of the transfer
counter and DISEL bit, the DMAC’s DTE bit is not subject to DTC control, and the write data
has priority. Consequently, an interrupt request may not be sent to the CPU when the DTC
transfer counter reaches 0.
• Chain Transfer
When chain transfer is used, clearing of the activation source or DTCER is performed when
the last of the chain of data transfers is executed. SCI and high-speed A/D converter
interrupt/activation sources, on the other hand, are cleared when the DTC reads or writes to the
prescribed register.
Therefore, when the DTC is activated by an interrupt or activation source, if a read/write of the
relevant register is not included in the last chained data transfer, the interrupt or activation
source will be retained.