Section 9 Data Transfer Controller (DTC)
Rev. 3.00 Mar 17, 2006 page 424 of 926
REJ09B0283-0300
First data
transfer register
information
Second data
transfer register
information
Chain transfer
(counter = 0)
Upper 8 bits
of DAR
Input buffer
Input circuit
Figure 9.12 Chain Transfer when Counter = 0
