Datasheet

Rev. 3.00 Mar 17, 2006 page xlv of l
Section 6 Bus Controller (BSC)
Table 6.1 Pin Configuration................................................................................................... 123
Table 6.2 Bus Specifications for Each Area (Basic Bus Interface)........................................ 155
Table 6.3 Data Buses Used and Valid Strobes....................................................................... 160
Table 6.4 Relation between Settings of Bits RMTS2 to RMTS0 and DRAM Space............. 173
Table 6.5 Relation between Settings of Bits MXC2 to MXC0 and Address Multiplexing.... 174
Table 6.6 DRAM Interface Pins............................................................................................. 175
Table 6.7 Relation between Settings of Bits RMTS2 to RMTS0 and Synchronous
DRAM Space ......................................................................................................... 198
Table 6.8 Relation between Settings of Bits MXC2 to MXC0 and Address Multiplexing.... 199
Table 6.9 Synchronous DRAM Interface Pins....................................................................... 201
Table 6.10 Setting CAS Latency.............................................................................................. 204
Table 6.11 Idle Cycles in Mixed Accesses to Normal Space and DRAM Continuous
Synchronous DRAM Space.................................................................................... 246
Table 6.12 Pin States in Idle Cycle .......................................................................................... 249
Table 6.13 Pin States in Bus Released State ............................................................................ 252
Section 7 DMA Controller (DMAC)
Table 7.1 Pin Configuration................................................................................................... 261
Table 7.2 Short Address Mode and Full Address Mode (Channel 0)..................................... 262
Table 7.3 DMAC Activation Sources .................................................................................... 286
Table 7.4 DMAC Transfer Modes.......................................................................................... 288
Table 7.5 Register Functions in Sequential Mode.................................................................. 290
Table 7.6 Register Functions in Idle Mode ............................................................................ 293
Table 7.7 Register Functions in Repeat Mode ....................................................................... 295
Table 7.8 Register Functions in Single Address Mode .......................................................... 298
Table 7.9 Register Functions in Normal Mode ...................................................................... 301
Table 7.10 Register Functions in Block Transfer Mode........................................................... 304
Table 7.11 DMAC Channel Priority Order .............................................................................. 325
Table 7.12 Interrupt Sources and Priority Order...................................................................... 329
Section 8 EXDMA Controller
Table 8.1 Pin Configuration................................................................................................... 337
Table 8.2 EXDMAC Transfer Modes .................................................................................... 350
Table 8.3 EXDMAC Channel Priority Order......................................................................... 366
Table 8.4 Interrupt Sources and Priority Order...................................................................... 395
Section 9 Data Transfer Controller (DTC)
Table 9.1 Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs................ 409
Table 9.2 Chain Transfer Conditions ..................................................................................... 412
Table 9.3 Register Function in Normal Mode........................................................................ 412