Datasheet

Section 9 Data Transfer Controller (DTC)
Rev. 3.00 Mar 17, 2006 page 410 of 926
REJ09B0283-0300
Origin of
Activation
Source
Activation
Source
Vector
Number
DTC
Vector Address DTCE
*
Priority
TPU_4 TGI4A 64 H'0480 DTCED1 High
TGI4B 65 H'0482 DTCED0
TPU_5 TGI5A 68 H'0488 DTCEE7
TGI5B 69 H'048A DTCEE6
TMR_0 CMIA0 72 H'0490 DTCEE3
CMIB0 73 H'0492 DTCEE2
TMR_1 CMIA1 76 H'0498 DTCEE1
CMIB1 77 H'049A DTCEE0
DMAC DMTEND0A 80 H'04A0 DTCEF7
DMTEND0B 81 H'04A2 DTCEF6
DMTEND1A 82 H'04A4 DTCEF5
DMTEND1B 83 H'04A6 DTCEF4
SCI_0 RXI0 89 H'04B2 DTCEF3
TXI0 90 H'04B4 DTCEF2
SCI_1 RXI1 93 H'04BA DTCEF1
TXI1 94 H'04BC DTCEF0
SCI_2 RXI2 97 H'04C2 DTCEG7
TXI2 98 H'04C4 DTCEG6 Low
Note: * DTCE bits with no corresponding interrupt are reserved, and should be written with 0.
When clearing the software standby state or all-module-clocks-stop mode with an
interrupt, write 0 to the corresponding DTCE bit.
9.5 Operation
The DTC stores register information in the on-chip RAM. When activated, the DTC reads register
information that is already stored in the on-chip RAM and transfers data on the basis of that
register information. After the data transfer, it writes updated register information back to the on-
chip RAM. Pre-storage of register information in the on-chip RAM makes it possible to transfer
data over any required number of channels. There are three transfer modes: normal mode, repeat
mode, and block transfer mode. Setting the CHNE bit to 1 makes it possible to perform a number
of transfers with a single activation (chain transfer). A setting can also be made to have chain
transfer performed only when the transfer counter value is 0. This enables DTC re-setting to be
performed by the DTC itself.