Datasheet

Section 9 Data Transfer Controller (DTC)
Rev. 3.00 Mar 17, 2006 page 404 of 926
REJ09B0283-0300
Bit Bit Name Initial Value R/W Description
0 Sz Undefined — DTC Data Transfer Size
Specifies the size of data to be transferred.
0: Byte-size transfer
1: Word-size transfer
Legend:
X: Don’t care
9.2.2 DTC Mode Register B (MRB)
MRB selects the DTC operating mode.
Bit Bit Name Initial Value R/W Description
7 CHNE Undefined — DTC Chain Transfer Enable
When this bit is set to 1, a chain transfer will be
performed. For details, refer to section 9.5.4, Chain
Transfer.
In data transfer with CHNE set to 1, determination of
the end of the specified number of transfers, clearing
of the activation source flag, and clearing of DTCER
is not performed.
6 DISEL Undefined — DTC Interrupt Select
When this bit is set to 1, a CPU interrupt request is
generated every time after a data transfer ends.
When this bit is set to 0, a CPU interrupt request is
generated at the time when the specified number of
data transfer ends.
5 CHNS Undefined — DTC Chain Transfer Select
Specifies the chain transfer condition.
0: Chain transfer every time
1: Chain transfer only when transfer counter = 0
4
to
0
— Undefined — Reserved
These bits have no effect on DTC operation, and
should always be written with 0.