Datasheet

Section 9 Data Transfer Controller (DTC)
Rev. 3.00 Mar 17, 2006 page 402 of 926
REJ09B0283-0300
Interrupt
request
Interrupt controller DTC
Internal address bus
DTC activation
request
Control logic
Register information
MRA MRB
CRA CRB
DAR SAR
CPU interrupt
request
On-chip
RAM
Internal data bus
Legend:
MRA, MRB
CRA, CRB
SAR
DAR
DTCERA to DTCERG
DTVECR
DTCERA
to
DTCERG
DTVECR
: DTC mode registers A and B
: DTC transfer count registers A and B
: DTC source address register
: DTC destination address register
: DTC enable registers A to G
: DTC vector register
Figure 9.1 Block Diagram of DTC
9.2 Register Descriptions
DTC has the following registers.
• DTC mode register A (MRA)
• DTC mode register B (MRB)
• DTC source address register (SAR)
• DTC destination address register (DAR)
• DTC transfer count register A (CRA)
• DTC transfer count register B (CRB)
These six registers cannot be directly accessed from the CPU. When activated, the DTC reads a set
of register information that is stored in an on-chip RAM to the corresponding DTC registers and
transfers data. After the data transfer, it writes a set of updated register information back to the
RAM.
• DTC enable registers A to G (DTCERA to DTCERG)
• DTC vector register (DTVECR)