Datasheet

Section 8 EXDMA Controller
Rev. 3.00 Mar 17, 2006 page 395 of 926
REJ09B0283-0300
8.5 Interrupt Sources
EXDMAC interrupt sources are a transfer end indicated by the transfer counter, and repeat area
overflow interrupts. Table 8.4 shows the interrupt sources and their priority order.
Table 8.4 Interrupt Sources and Priority Order
Interrupt Interrupt source Interrupt Priority
EXDMTEND0 Transfer end indicated by channel 0 transfer counter
Channel 0 source address repeat area overflow
Channel 0 destination address repeat area overflow
High
EXDMTEND1 Transfer end indicated by channel 1 transfer counter
Channel 1 source address repeat area overflow
Channel 1 destination address repeat area overflow
EXDMTEND2 Transfer end indicated by channel 2 transfer counter
Channel 2 source address repeat area overflow
Channel 2 destination address repeat area overflow
EXDMTEND3 Transfer end indicated by channel 3 transfer counter
Channel 3 source address repeat area overflow
Channel 3 destination address repeat area overflow Low
Interrupt sources can be enabled or disabled by means of the EDIE bit in EDMDR for the relevant
channel, and can be sent to the interrupt controller independently. The relative priority order of the
channels is determined by the interrupt controller (see table 8.4).
Figure 8.45 shows the transfer end interrupt logic. A transfer end interrupt is generated whenever
the EDIE bit is set to 1 while the IRF bit is set to 1 in EDMDR.
Transfer end interrupt
IRF bit
EDIE bit
Figure 8.45 Transfer End Interrupt Logic