Datasheet

Section 8 EXDMA Controller
Rev. 3.00 Mar 17, 2006 page 391 of 926
REJ09B0283-0300
φ pin
EDREQ
EDRAK
Bus cycle
CPU
operation
EDACK
ETEND
1-block-size transfer period
1 bus cycle
CPU
cycle
CPU
cycle
External
space
External
space
CPU
cycle
CPU
cycle
CPU
cycle
CPU
cycle
CPU
cycle
CPU
cycle
External
space
External
space
External
space
External
space
External
space
External
space
1 bus cycle
1 bus cycle
Last transfer
in block
EXDMA
transfer cycle
EXDMA
transfer cycle
EXDMA
transfer cycle
EXDMA
transfer cycle
EXDMA
transfer cycle
EXDMA
transfer cycle
EXDMA
transfer cycle
Repeated
Figure 8.43 External Request/Cycle Steal Mode/Block Transfer Mode
(CPU Cycles/Single Address Mode/Low Level Sensing/BGUP = 1)