Datasheet
Section 8 EXDMA Controller
Rev. 3.00 Mar 17, 2006 page 390 of 926
REJ09B0283-0300
φ pin
EDREQ
EDRAK
Bus cycle
CPU
operation
ETEND
1-block-size transfer period
1 bus cycle
CPU
cycle
CPU
cycle
CPU
cycle
CPU
cycle
CPU
cycle
CPU
cycle
CPU
cycle
CPU
cycle
External
space
External
space
External
space
External
space
EXDMA
read
EXDMA
write
EXDMA
read
EXDMA
read
EXDMA
write
EXDMA
read
EXDMA
write
1 bus cycle
1 bus cycle
Last transfer
in block
External
space
External
space
External
space
External
space
Repeated
Figure 8.42 External Request/Cycle Steal Mode/Block Transfer Mode
(CPU Cycles/Dual Address Mode/Low Level Sensing/BGUP = 1)