Datasheet

Section 8 EXDMA Controller
Rev. 3.00 Mar 17, 2006 page 388 of 926
REJ09B0283-0300
φ pin
EDREQ EDRAK EDACK Bus cycle ETEND
Bus release Bus release
Last transfer
in block
1-block-size transfer period
Last block
Last transfer cycle3 cycles
EXDMA single
transfer cycle
EXDMA single
transfer cycle
EXDMA single
transfer cycle
EXDMA single
transfer cycle
EXDMA single
transfer cycle
Repeated Repeated
Bus release
Figure 8.40 External Request/Cycle Steal Mode/Block Transfer Mode
(No Contention/Single Address Mode/Falling Edge Sensing/BGUP = 0)