Datasheet

Rev. 3.00 Mar 17, 2006 page xlii of l
Section 22 Power-Down Modes
Figure 22.1 Mode Transitions................................................................................................. 821
Figure 22.2 Software Standby Mode Application Example.................................................... 829
Figure 22.3 Hardware Standby Mode Timing......................................................................... 830
Section 24 Electrical Characteristics
Figure 24.1 Output Load Circuit............................................................................................. 870
Figure 24.2 System Clock Timing .......................................................................................... 871
Figure 24.3 SDRAMφ Timing ................................................................................................ 872
Figure 24.4 (1) Oscillation Stabilization Timing........................................................................ 872
Figure 24.4 (2) Oscillation Stabilization Timing........................................................................ 873
Figure 24.5 Reset Input Timing .............................................................................................. 874
Figure 24.6 Interrupt Input Timing ......................................................................................... 875
Figure 24.7 Basic Bus Timing: Two-State Access.................................................................. 879
Figure 24.8 Basic Bus Timing: Three-State Access................................................................ 880
Figure 24.9 Basic Bus Timing: Three-State Access, One Wait............................................... 881
Figure 24.10 Basic Bus Timing: Two-State Access (CS Assertion Period Extended).............. 882
Figure 24.11 Basic Bus Timing: Three-State Access (CS Assertion Period Extended)............ 883
Figure 24.12 Burst ROM Access Timing: One-State Burst Access.......................................... 884
Figure 24.13 Burst ROM Access Timing: Two-State Burst Access ......................................... 885
Figure 24.14 DRAM Access Timing: Two-State Access.......................................................... 886
Figure 24.15 DRAM Access Timing: Two-State Access, One Wait ........................................ 887
Figure 24.16 DRAM Access Timing: Two-State Burst Access................................................ 888
Figure 24.17 DRAM Access Timing: Three-State Access (RAST = 1).................................... 889
Figure 24.18 DRAM Access Timing: Three-State Access, One Wait ...................................... 890
Figure 24.19 DRAM Access Timing: Three-State Burst Access.............................................. 891
Figure 24.20 CAS-Before-RAS Refresh Timing ...................................................................... 892
Figure 24.21 CAS-Before-RAS Refresh Timing (with Wait Cycle Insertion).......................... 892
Figure 24.22 Self-Refresh Timing (Return from Software Standby Mode: RAST = 0) ........... 893
Figure 24.23 Self-Refresh Timing (Return from Software Standby Mode: RAST = 1) ........... 893
Figure 24.24 External Bus Release Timing............................................................................... 894
Figure 24.25 External Bus Request Output Timing.................................................................. 894
Figure 24.26 Synchronous DRAM Basic Access Timing (CAS Latency 2)............................. 895
Figure 24.27 Synchronous DRAM Self-Refresh Timing.......................................................... 896
Figure 24.28 Read Data: Two-State Expansion (CAS Latency 2)............................................ 897
Figure 24.29 DMAC and EXDMAC Single Address Transfer Timing: Two-State Access ..... 899
Figure 24.30 DMAC and EXDMAC Single Address Transfer Timing: Three-State Access ... 900
Figure 24.31 DMAC and EXDMAC TEND/ETEND Output Timing...................................... 901
Figure 24.32 DMAC and EXDMAC DREQ/EDREQ Input Timing ........................................ 901
Figure 24.33 EXDMAC EDRAK Output Timing..................................................................... 901
Figure 24.34 I/O Port Input/Output Timing.............................................................................. 903