Datasheet

Section 8 EXDMA Controller
Rev. 3.00 Mar 17, 2006 page 387 of 926
REJ09B0283-0300
φ pin EDREQ EDRAK ETEND Bus cycle EDA bit
Bus release Bus release
EXDMA
read
EXDMA
write
EXDMA
read
EXDMA
write
EXDMA
read
EXDMA
write
EXDMA
read
EXDMA
write
EXDMA
read
EXDMA
write
01
Last transfer
in block
1-block-size transfer period
Last block
Last transfer cycle
3 cycles
Repeated
Bus release
Repeated
Figure 8.39 External Request/Cycle Steal Mode/Block Transfer Mode
(No Contention/Dual Address Mode/Low Level Sensing/BGUP = 0)