Datasheet

Section 8 EXDMA Controller
Rev. 3.00 Mar 17, 2006 page 386 of 926
REJ09B0283-0300
φ pin
Original
channel
EDREQ
Original
channel
EDRAK
Other
channel
EDREQ
Other
channel
EDRAK
Bus cycle
3 cycles
1 cycle 1 cycle
EXDMA transfer
cycle
Bus release
Other channel
transfer cycle
EXDMA
read
EXDMA
write
EXDMA
read
EXDMA
write
Bus
release
Bus
release
Figure 8.38 External Request/Cycle Steal Mode/Normal Transfer Mode Contention
with Another Channel/Dual Address Mode/Low Level Sensing
External Request/Cycle Steal Mode/Block Transfer Mode: In block transfer mode, transfer of
one block is performed continuously in the same way as in burst mode. The timing of the start of
the next block transfer is the same as in normal transfer mode.
If a transfer request is generated for another channel, an EXDMA cycle for the other channel is
generated before the next block transfer.
The EDREQ pin sensing timing is different for low level sensing and falling edge sensing. The
same applies to transfer request acceptance and transfer start timing.
Figures 8.39 to 8.44 show operation timing examples for various conditions.