Datasheet

Section 8 EXDMA Controller
Rev. 3.00 Mar 17, 2006 page 384 of 926
REJ09B0283-0300
External Request/Cycle Steal Mode/Normal Transfer Mode: In external request mode, an
EXDMA transfer cycle is started a minimum of three cycles after a transfer request is accepted.
The next transfer request is accepted after the end of a one-transfer-unit EXDMA cycle. For
external bus space CPU cycles, at least two bus cycles are generated before the next EXDMA
cycle.
If a transfer request is generated for another channel, an EXDMA cycle for the other channel is
generated before the next EXDMA cycle.
The EDREQ pin sensing timing is different for low level sensing and falling edge sensing. The
same applies to transfer request acceptance and transfer start timing.
Figures 8.35 to 8.38 show operation timing examples for various conditions.
φ pin
EDREQ
EDRAK
ETEND
Bus cycle
EDA bit
Bus release Bus release Bus release
EXDMA
read
EXDMA
write
EXDMA
read
EXDMA
write
01
Last transfer cycle3 cycles
Figure 8.35 External Request/Cycle Steal Mode/Normal Transfer Mode
(No Contention/Dual Address Mode/Low Level Sensing)