Datasheet

Rev. 3.00 Mar 17, 2006 page xli of l
Figure 16.3 External Trigger Input Timing............................................................................. 756
Figure 16.4 A/D Conversion Accuracy Definitions ................................................................ 758
Figure 16.5 A/D Conversion Accuracy Definitions ................................................................ 758
Figure 16.6 Example of Analog Input Circuit......................................................................... 759
Figure 16.7 Example of Analog Input Protection Circuit ....................................................... 761
Figure 16.8 Analog Input Pin Equivalent Circuit.................................................................... 762
Section 17 D/A Converter
Figure 17.1 Block Diagram of D/A Converter........................................................................ 764
Figure 17.2 Example of D/A Converter Operation ................................................................. 770
Section 19 Flash Memory (F-ZTAT Version)
Figure 19.1 Block Diagram of Flash Memory ....................................................................... 774
Figure 19.2 Flash Memory State Transitions .......................................................................... 775
Figure 19.3 Boot Mode ........................................................................................................... 776
Figure 19.4 User Program Mode............................................................................................. 777
Figure 19.5 384-kbyte Flash Memory Block Configuration (Modes 3, 4, and 7)................... 779
Figure 19.6 256-kbyte Flash Memory Block Configuration (Modes 4, 7, 10, and 11)........... 780
Figure 19.7 Programming/Erasing Flowchart Example in User Program Mode..................... 793
Figure 19.8 Flowchart for Flash Memory Emulation in RAM................................................ 794
Figure 19.9 Example of RAM Overlap Operation.................................................................. 795
Figure 19.10 Program/Program-Verify Flowchart.................................................................... 797
Figure 19.11 Erase/Erase-Verify Flowchart.............................................................................. 799
Figure 19.12 Power-On/Off Timing (H8S/2678 Group)........................................................... 804
Figure 19.13 Power-On/Off Timing (H8S/2678R Group) ........................................................ 805
Figure 19.14 Mode Transition Timing
(Example: Boot Mode → User Mode ↔ User Program Mode) .......................... 806
Section 20 Masked ROM
Figure 20.1 Block Diagram of 256-kbyte Masked ROM (HD6432676)................................. 809
Figure 20.2 Block Diagram of 128-kbyte Masked ROM (HD6432675)................................. 809
Figure 20.3 Block Diagram of 64-kbyte Masked ROM (HD6432673)................................... 810
Section 21 Clock Pulse Generator
Figure 21.1 Block Diagram of Clock Pulse Generator............................................................ 811
Figure 21.2 Connection of Crystal Resonator (Example) ....................................................... 814
Figure 21.3 Crystal Resonator Equivalent Circuit................................................................... 814
Figure 21.4 External Clock Input (Examples)......................................................................... 815
Figure 21.5 External Clock Input Timing ............................................................................... 816
Figure 21.6 Note on Board Design for Oscillation Circuit...................................................... 818
Figure 21.7 Recommended External Circuitry for PLL Circuit.............................................. 818