Datasheet

Section 8 EXDMA Controller
Rev. 3.00 Mar 17, 2006 page 377 of 926
REJ09B0283-0300
Single Address Mode (Write): Figure 8.24 shows an example of transfer when ETEND output is
enabled, and byte-size, single address mode transfer (write) is performed from an external device
to external 8-bit, 2-state access space.
HWR
ETEND
Address bus
Bus release Bus release Bus releaseLast
transfer
cycle
DMA write
EDACK
DMA writeDMA writeDMA write
Bus releaseBus release
LWR
φ
Figure 8.24 Example of Single Address Mode (Byte Write) Transfer
Figure 8.25 shows an example of transfer when ETEND output is enabled, and word-size, single
address mode transfer (write) is performed from an external device to external 8-bit, 2-state access
space.
DMA write
HWR
ETEND
Address bus
Bus release Bus release Bus
release
Last transfer cycle
EDACK
Bus release
DMA writeDMA write
LWR
φ
Figure 8.25 Example of Single Address Mode (Word Write) Transfer