Datasheet

Section 8 EXDMA Controller
Rev. 3.00 Mar 17, 2006 page 376 of 926
REJ09B0283-0300
8.4.10 EXDMAC Bus Cycles (Single Address Mode)
Single Address Mode (Read): Figure 8.22 shows an example of transfer when ETEND output is
enabled, and byte-size, single address mode transfer (read) is performed from external 8-bit, 2-
state access space to an external device.
RD
ETEND
Address bus
Bus release Bus release Bus releaseLast
transfer
cycle
DMA read
EDACK
DMA readDMA readDMA read
Bus releaseBus release
φ
Figure 8.22 Example of Single Address Mode (Byte Read) Transfer
Figure 8.23 shows an example of transfer when ETEND output is enabled, and word-size, single
address mode transfer (read) is performed from external 8-bit, 2-state access space to an external
device.
DMA read
RD
ETEND
Address bus
Bus release Bus release Bus
release
Last transfer cycle
EDACK
Bus release
DMA readDMA read
φ
Figure 8.23 Example of Single Address Mode (Word Read) Transfer
After one byte or word has been transferred in response to one transfer request, the bus is released.
While the bus is released, one or more CPU, DMAC, or DTC bus cycles are initiated.