Datasheet

Section 8 EXDMA Controller
Rev. 3.00 Mar 17, 2006 page 375 of 926
REJ09B0283-0300
DMA read DMA write
φ
Address bus
EDREQ
Idle Write
Bus release
DMA control
Channel
WriteIdleRead
Bus release DMA read DMA write
One block transfer One block transfer
Idle
Transfer
destination
Transfer source
Transfer
destination
Transfer source
[1] [3][2] [4] [6][5] [7]
Acceptance
resumed
Acceptance
resumed
Bus release
[1] Acceptance after transfer enabling; EDREQ pin low level is sampled at rise of φ, and request is held.
[2], [5] Request is cleared at end of next bus cycle, and activation is started in EXDMAC.
[3], [6] DMA cycle is started.
[4], [7] Acceptance is resumed after completion of dead cycle.
(As in [1], EDREQ pin low level is sampled at rise of φ, and request is held.)
Minimum 3 cycles
Request Request
Read
Minimum 3 cycles
Request clearance period Request clearance period
Figure 8.21 Example of Block Transfer Mode Transfer Activated by EDREQ
EDREQEDREQ
EDREQ Pin Low Level
EDREQ pin sampling is performed in each cycle starting at the next rise of φ after the end of the
EDMDR write cycle for setting the transfer-enabled state.
When a low level is sampled at the EDREQ pin while acceptance via the EDREQ pin is possible,
the request is held within the EXDMAC. Then when activation is initiated within the EXDMAC,
the request is cleared. At the end of the write cycle, acceptance resumes and EDREQ pin low level
sampling is performed again; this sequence of operations is repeated until the end of the transfer.