Datasheet

Section 8 EXDMA Controller
Rev. 3.00 Mar 17, 2006 page 367 of 926
REJ09B0283-0300
Channel 0 transfer
Idle
Bus
release
Address bus
EXDMA control
Channel 0
Channel 1
Channel 1 transfer Channel 2 transfer
Channel 2Channel 0 Channel 1
Channel 2Channel 0
Request
held
Selected
Request
held
Request
held
Not
selected
Selected
Channel 1
Request cleared
Request cleared
Request cleared
Bus
release
Channel 2
φ
Figure 8.13 Example of Channel Priority Timing
Transfer Requests from Multiple Channels in Auto Request Cycle Steal Mode: If transfer
requests for different channels are issued during a transfer in auto request cycle steal mode, the
operation depends on the channel priority. If the channel that made the transfer request is of higher
priority than the channel currently performing transfer, the channel that made the transfer request
is selected.
If the channel that made the transfer request is of lower priority than the channel currently
performing transfer, that channel’s transfer request is held pending, and the currently transferring
channel remains selected.
The selected channel begins transfer after the currently transferring channel releases the bus. If
there is a bus request from a bus mastership other than the EXDMAC at this time, a cycle for the
other bus mastership is initiated. If there is no other bus request, the bus is released for one cycle.
Figure 8.14 shows examples of transfer timing in cases that include auto request cycle steal mode.