Datasheet

Section 8 EXDMA Controller
Rev. 3.00 Mar 17, 2006 page 364 of 926
REJ09B0283-0300
23 0
0EDTCR
Fixed
23 0
0
Before update After update
23 0
1 to H'FFFFFFEDTCR
–1
23 0
0 to H'FFFFFE
EDTCR
EDTCR in normal transfer mode
EDTCR in block transfer mode
Fixed
Before update After update
23 15 016
1 to H'FFFF
Block
size
EDTCR
–1
23 15 016
0
Block
size
23 15 016
0 to H'FFFE
Block
size
23 15 016
0
Block
size
Figure 8.11 EDTCR Update Operations in Normal Transfer Mode and
Block Transfer Mode
EDA Bit in EDMDR: The EDA bit in EDMDR is written to by the CPU to control enabling and
disabling of data transfer, but may be cleared automatically by the EXDMAC due to the DMA
transfer status. There are also periods during transfer when a 0-write to the EDA bit by the CPU is
not immediately effective.
Conditions for EDA bit clearing by the EXDMAC include the following:
• When the EDTCR value changes from 1 to 0, and transfer ends
• When a repeat area overflow interrupt is requested, and transfer ends
• When an NMI interrupt is generated, and transfer halts
• A reset
• Hardware standby mode
• When 0 is written to the EDA bit, and transfer halts
When transfer is halted by writing 0 to the EDA bit, the EDA bit remains at 1 during the DMA
transfer period. In block transfer mode, since a block-size transfer is carried out without
interruption, the EDA bit remains at 1 from the time 0 is written to it until the end of the current
block-size transfer.