Datasheet

Section 8 EXDMA Controller
Rev. 3.00 Mar 17, 2006 page 360 of 926
REJ09B0283-0300
The source address repeat area is specified by bits SARA4 to SARA0 in EDACR, and the
destination address repeat area by bits DARA4 to DARA0 in EDACR. The size of each repeat
area can be specified independently.
When the address register value is the last address in the repeat area and repeat area overflow
occurs, DMA transfer can be temporarily halted and an interrupt request sent to the CPU. If the
SARIE bit in EDACR is set to 1, when the source address register overflows the repeat area, the
IRF bit is set to 1 and the EDA bit cleared to 0 in EDMDR, and transfer is terminated. If EDIE = 1
in EDMDR, an interrupt is requested. If the DARIE bit in EDACR is set to 1, the above applies to
the destination address register.
If the EDA bit in EDMDR is set to 1 during interrupt generation, transfer is resumed. Figure 8.9
illustrates the operation of the repeat area function.
External memory
Repeated
Repeat area overflow
interrupt can be
requested
Range of
EDSAR values
H'23FFFE
H'23FFFF
H'240000
H'240001
H'240002
H'240003
H'240004
H'240005
H'240006
H'240007
H'240008
H'240009
H'240000
H'240001
H'240002
H'240003
H'240004
H'240005
H'240006
H'240007
:
:
When lower 3 bits (8-byte area) of EDSAR are designated as repeat area
(SARA4 to SARA0 = 3)
Figure 8.9 Example of Repeat Area Function Operation
Caution is required when the repeat area overflow interrupt function is used together with block
transfer mode. If transfer is always terminated when repeat area overflow occurs in block transfer