Datasheet

Section 8 EXDMA Controller
Rev. 3.00 Mar 17, 2006 page 358 of 926
REJ09B0283-0300
Read Write Read Write
EXDMA
transfer cycle
Last EXDMA
transfer cycle
Bus cycle
ETEND
Transfer conditions:
Dual address mode, auto request mode
EXDMA EXDMA
EDRAK
EDREQ
Bus cycle
EDACK
Transfer conditions:
Single address mode, external request mode
Figure 8.7 Examples of Timing in Normal Transfer Mode
Block Transfer Mode: In block transfer mode, the number of bytes or words specified by the
block size is transferred in response to one transfer request. The upper 8 bits of EDTCR specify
the block size, and the lower 16 bits function as a 16-bit transfer counter. A block size of 1 to 256
can be specified. During transfer of a block, transfer requests for other higher-priority channels are
held pending. When transfer of one block is completed, the bus is released in the next cycle.
When the BGUP bit is set to 1 in EDMDR, the bus is released if a bus request is issued by another
bus mastership during block transfer.
Address register values are updated in the same way as in normal mode. There is no function for
restoring the initial address register values after each block transfer.
The ETEND signal is output for each block transfer in the DMA transfer cycle in which the block
ends. The EDRAK signal is output once for one transfer request (for transfer of one block).