Datasheet

Rev. 3.00 Mar 17, 2006 page xxxix of l
Figure 12.8 Setup Procedure for Non-Overlapping Pulse Output (Example)......................... 621
Figure 12.9 Non-Overlapping Pulse Output Example (Four-Phase Complementary) ............ 622
Figure 12.10 Inverted Pulse Output (Example)......................................................................... 624
Figure 12.11 Pulse Output Triggered by Input Capture (Example) .......................................... 625
Section 13 8-Bit Timers (TMR)
Figure 13.1 Block Diagram of 8-Bit Timer Module ............................................................... 628
Figure 13.2 Example of Pulse Output ..................................................................................... 637
Figure 13.3 Count Timing for Internal Clock Input................................................................ 637
Figure 13.4 Count Timing for External Clock Input............................................................... 638
Figure 13.5 Timing of CMF Setting........................................................................................ 638
Figure 13.6 Timing of Timer Output....................................................................................... 639
Figure 13.7 Timing of Compare Match Clear......................................................................... 639
Figure 13.8 Timing of Clearance by External Reset ............................................................... 640
Figure 13.9 Timing of OVF Setting........................................................................................ 640
Figure 13.10 Contention between TCNT Write and Clear........................................................ 643
Figure 13.11 Contention between TCNT Write and Increment ................................................ 644
Figure 13.12 Contention between TCOR Write and Compare Match ...................................... 645
Section 14 Watchdog Timer
Figure 14.1 Block Diagram of WDT....................................................................................... 650
Figure 14.2 Operation in Watchdog Timer Mode ................................................................... 655
Figure 14.3 Operation in Interval Timer Mode....................................................................... 656
Figure 14.4 Writing to TCNT, TCSR, and RSTCSR ............................................................. 657
Figure 14.5 Contention between TCNT Write and Increment ................................................ 658
Figure 14.6 Circuit for System Reset by WDTOVF Signal (Example) .................................. 659
Section 15 Serial Communication Interface (SCI, IrDA)
Figure 15.1 Block Diagram of SCI ......................................................................................... 663
Figure 15.2 Data Format in Asynchronous Communication
(Example with 8-Bit Data, Parity, Two Stop Bits) .............................................. 691
Figure 15.3 Receive Data Sampling Timing in Asynchronous Mode..................................... 693
Figure 15.4 Relation between Output Clock and Transfer Data Phase
(Asynchronous Mode) ......................................................................................... 694
Figure 15.5 Sample SCI Initialization Flowchart.................................................................... 695
Figure 15.6 Example of Operation in Transmission in Asynchronous Mode
(Example with 8-Bit Data, Parity, One Stop Bit)................................................. 696
Figure 15.7 Sample Serial Transmission Flowchart................................................................ 697
Figure 15.8 Example of SCI Operation in Reception
(Example with 8-Bit Data, Parity, One Stop Bit)................................................. 698
Figure 15.9 Sample Serial Reception Data Flowchart (1)....................................................... 700