Datasheet

Section 8 EXDMA Controller
Rev. 3.00 Mar 17, 2006 page 357 of 926
REJ09B0283-0300
When the BGUP bit is set to 1 in EDMDR, the bus is released if a bus request is issued by another
bus mastership during burst transfer. If there is no bus request, burst transfer is executed even if
the BGUP bit is set to 1.
Figure 8.6 shows examples of the timing in burst mode.
CPU CPU CPU CPU
Bus cycle
EXDMAC operates alternately with CPU
EXDMAC EXDMAC EXDMAC
Transfer conditions:
Auto request mode, BGUP = 1
CPU CPU
CPU CPU
Bus cycle
CPU cycle not generated
EXDMAC EXDMAC EXDMAC
Transfer conditions:
Auto request mode, BGUP = 0
Figure 8.6 Examples of Timing in Burst Mode
8.4.5 Transfer Modes
There are two transfer modes: normal transfer mode and block transfer mode. When the activation
source is an external request, either normal transfer mode or block transfer mode can be selected.
When the activation source is an auto request, normal transfer mode is used.
Normal Transfer Mode: In normal transfer mode, transfer of one transfer unit is processed in
response to one transfer request. EDTCR functions as a 24-bit transfer counter.
The ETEND signal is output only for the last DMA transfer. The EDRAK signal is output each
time a transfer request is accepted and transfer processing is started.
Figure 8.7 shows examples of DMA transfer timing in normal transfer mode.