Datasheet

Section 8 EXDMA Controller
Rev. 3.00 Mar 17, 2006 page 354 of 926
REJ09B0283-0300
EXDMA cycle
EDSAR
Address to external memory space
RD signal to external memory space
Data output from external memory
Address bus
φ
φ
RD
WR
EDACK
ETEND
Data bus
EXDMA cycle
EDDAR
Address to external memory space
WR signal to external memory space
Address bus
Transfer from external memory to external device with DACK
Transfer from external device with DACK to external memory
RD
WR
EDACK
ETEND
Data bus
Data output from external device
with DACK
Figure 8.4 Example of Timing in Single Address Mode