Datasheet

Section 8 EXDMA Controller
Rev. 3.00 Mar 17, 2006 page 338 of 926
REJ09B0283-0300
8.3 Register Descriptions
The EXDMAC has the following registers.
• EXDMA source address register_0 (EDSAR_0)
• EXDMA destination address register_0 (EDDAR_0)
• EXDMA transfer count register_0 (EDTCR_0)
• EXDMA mode control register_0 (EDMDR_0)
• EXDMA address control register_0 (EDACR_0)
• EXDMA source address register_1 (EDSAR_1)
• EXDMA destination address register_1 (EDDAR_1)
• EXDMA transfer count register_1 (EDTCR_1)
• EXDMA mode control register_1 (EDMDR_1)
• EXDMA address control register_1 (EDACR_1)
• EXDMA source address register_2 (EDSAR_2)
• EXDMA destination address register_2 (EDDAR_2)
• EXDMA transfer count register_2 (EDTCR_2)
• EXDMA mode control register_2 (EDMDR_2)
• EXDMA address control register_2 (EDACR_2)
• EXDMA source address register_3 (EDSAR_3)
• EXDMA destination address register_3 (EDDAR_3)
• EXDMA transfer count register_3 (EDTCR_3)
• EXDMA mode control register_3 (EDMDR_3)
• EXDMA address control register_3 (EDACR_3)
8.3.1 EXDMA Source Address Register (EDSAR)
EDSAR is a 32-bit readable/writable register that specifies the transfer source address. An address
update function is provided that updates the register contents to the next transfer source address
each time transfer processing is performed. In single address mode, the EDSAR value is ignored
when a device with DACK is specified as the transfer source. The upper 8 bits of EDSAR are
reserved; they are always read as 0 and cannot be modified.
EDSAR can be read at all times by the CPU. When reading EDSAR for a channel on which
EXDMA transfer processing is in progress, a longword-size read must be executed. Do not write
to EDSAR for a channel on which EXDMA transfer is in progress. The initial values of EDSAR
are undefined.