Datasheet

Section 8 EXDMA Controller
Rev. 3.00 Mar 17, 2006 page 336 of 926
REJ09B0283-0300
Bus controller
Internal data bus
Interrupt request
signals to CPU
for individual
channels
External pins
EDMDR
EDACR
EDTCR
EDDAR
EDSAR
Processor
Address buffer
Data buffer
Control logic
Module data bus
EDREQ
EDRAK
ETEND
EDACK
Legend:
EDSAR: EXDMA source address register
EDDAR: EXDMA destination address register
EDTCR: EXDMA transfer count register
EDMDR: EXDMA mode control register
EDACR: EXDMA address control register
Figure 8.1 Block Diagram of EXDMAC