Datasheet

Section 7 DMA Controller (DMAC)
Rev. 3.00 Mar 17, 2006 page 333 of 926
REJ09B0283-0300
φ
Internal address
Internal read signal
External address
HWR, LWR
Internal write signal
TEND
Not output
DMA
read
External write by CPU, etc.
DMA
write
Figure 7.41 Example in Which Low Level Is Not Output at TEND
TENDTEND
TEND Pin
7.7.5 Activation by Falling Edge on DREQ
DREQDREQ
DREQ Pin
DREQ pin falling edge detection is performed in synchronization with DMAC internal operations.
The operation is as follows:
[1] Activation request wait state: Waits for detection of a low level on the DREQ pin, and
switches to [2].
[2] Transfer wait state: Waits for DMAC data transfer to become possible, and switches to [3].
[3] Activation request disabled state: Waits for detection of a high level on the DREQ pin, and
switches to [1].
After DMAC transfer is enabled, a transition is made to [1]. Thus, initial activation after transfer is
enabled is performed on detection of a low level.