Datasheet

Section 7 DMA Controller (DMAC)
Rev. 3.00 Mar 17, 2006 page 325 of 926
REJ09B0283-0300
φ
Internal address
Internal read signal
RD
DACK
External address
DMA
read
DMA
single
CPU
read
DMA
single
CPU
read
Figure 7.33 Example of Single Address Transfer Using Write Data Buffer Function
When the write data buffer function is activated, the DMAC recognizes that the bus cycle
concerned has ended, and starts the next operation. Therefore, DREQ pin sampling is started one
state after the start of the DMA write cycle or single address transfer.
7.5.12 Multi-Channel Operation
The DMAC channel priority order is: channel 0 > channel 1, and channel A > channel B. Table
7.11 summarizes the priority order for DMAC channels.
Table 7.11 DMAC Channel Priority Order
Short Address Mode Full Address Mode Priority
Channel 0A Channel 0 High
Channel 0B
Channel 1A Channel 1
Channel 1B Low
If transfer requests are issued simultaneously for more than one channel, or if a transfer request for
another channel is issued during a transfer, when the bus is released, the DMAC selects the
highest-priority channel from among those issuing a request according to the priority order shown
in table 7.11. During burst transfer, or when one block is being transferred in block transfer, the