Datasheet

Section 7 DMA Controller (DMAC)
Rev. 3.00 Mar 17, 2006 page 323 of 926
REJ09B0283-0300
Figure 7.31 shows an example of single address mode transfer activated by the DREQ pin low
level.
φ
DREQ
Bus release DMA single
Address bus
DMA control
Channel
[2]
DACK
Transfer source/
destination
Idle Idle Idle
[1] [3] [5][4] [6] [7]
Acceptance resumesAcceptance resumes
Bus release DMA single
Bus
release
Transfer source/
destination
Request Request
Request clear
period
Request clear
period
Single
Single
Minimum of
2 cycles
Minimum of
2 cycles
[1] Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of φ,
and the request is held.
[2] [5] The request is cleared at the next bus break, and activation is started in the DMAC.
[3] [6] The DMAC cycle is started.
[4] [7] Acceptance is resumed after the single cycle is completed.
(As in [1], the DREQ pin low level is sampled on the rising edge of φ, and the request is held.)
Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible.
Figure 7.31 Example of DREQ
DREQDREQ
DREQ Pin Low Level Activated Single Address Mode Transfer
DREQ pin sampling is performed every cycle, with the rising edge of the next φ cycle after the
end of the DMABCR write cycle for setting the transfer enabled state as the starting point.
When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is
possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the