Datasheet

Section 7 DMA Controller (DMAC)
Rev. 3.00 Mar 17, 2006 page 320 of 926
REJ09B0283-0300
Single Address Mode (Write): Figure 7.28 shows a transfer example in which TEND output is
enabled and byte-size single address mode transfer (write) is performed from an external device to
external 8-bit, 2-state access space.
DMA write
φ
Address bus
DMA
dead
HWR
DACK
TEND
Bus
release
LWR
DMA write DMA write DMA write
Bus
release
Bus
release
Bus
release
Bus
release
Last transfer
cycle
Figure 7.28 Example of Single Address Mode Transfer (Byte Write)