Datasheet

Section 7 DMA Controller (DMAC)
Rev. 3.00 Mar 17, 2006 page 318 of 926
REJ09B0283-0300
7.5.10 DMA Bus Cycles (Single Address Mode)
Single Address Mode (Read): Figure 7.26 shows a transfer example in which TEND output is
enabled and byte-size single address mode transfer (read) is performed from external 8-bit, 2-state
access space to an external device.
DMA read
φ
Address bus
DMA
dead
RD
DACK
TEND
Bus
release
DMA read DMA read DMA read
Bus
release
Bus
release
Bus
release
Bus
release
Last transfer
cycle
Figure 7.26 Example of Single Address Mode Transfer (Byte Read)