Datasheet

Rev. 3.00 Mar 17, 2006 page xxxv of l
Figure 7.29 Example of Single Address Mode Transfer (Word Write) .................................. 321
Figure 7.30 Example of DREQ Pin Falling Edge Activated Single Address Mode Transfer 322
Figure 7.31 Example of DREQ Pin Low Level Activated Single Address Mode Transfer .... 323
Figure 7.32 Example of Dual Address Transfer Using Write Data Buffer Function .............. 324
Figure 7.33 Example of Single Address Transfer Using Write Data Buffer Function............ 325
Figure 7.34 Example of Multi-Channel Transfer.................................................................... 326
Figure 7.35 Example of Procedure for Continuing Transfer on Channel Interrupted
by NMI Interrupt.................................................................................................. 327
Figure 7.36 Example of Procedure for Forcibly Terminating DMAC Operation ................... 328
Figure 7.37 Example of Procedure for Clearing Full Address Mode...................................... 328
Figure 7.38 Block Diagram of Transfer End/Transfer Break Interrupt................................... 329
Figure 7.39 DMAC Register Update Timing.......................................................................... 330
Figure 7.40 Contention between DMAC Register Update and CPU Read ............................. 331
Figure 7.41 Example in Which Low Level Is Not Output at TEND Pin................................. 333
Section 8 EXDMA Controller
Figure 8.1 Block Diagram of EXDMAC .............................................................................. 336
Figure 8.2 Example of Timing in Dual Address Mode......................................................... 352
Figure 8.3 Data Flow in Single Address Mode..................................................................... 353
Figure 8.4 Example of Timing in Single Address Mode....................................................... 354
Figure 8.5 Example of Timing in Cycle Steal Mode............................................................. 356
Figure 8.6 Examples of Timing in Burst Mode..................................................................... 357
Figure 8.7 Examples of Timing in Normal Transfer Mode................................................... 358
Figure 8.8 Example of Timing in Block Transfer Mode....................................................... 359
Figure 8.9 Example of Repeat Area Function Operation...................................................... 360
Figure 8.10 Example of Repeat Area Function Operation in Block Transfer Mode............... 361
Figure 8.11 EDTCR Update Operations in Normal Transfer Mode
and Block Transfer Mode .................................................................................... 364
Figure 8.12 Procedure for Changing Register Settings in Operating Channel........................ 365
Figure 8.13 Example of Channel Priority Timing................................................................... 367
Figure 8.14 Examples of Channel Priority Timing ................................................................. 368
Figure 8.15 Example of Normal Transfer Mode (Cycle Steal Mode) Transfer....................... 369
Figure 8.16 Example of Normal Transfer Mode (Burst Mode) Transfer................................ 370
Figure 8.17 Example of Block Transfer Mode (Cycle Steal Mode) Transfer ......................... 371
Figure 8.18 Example of Normal Mode Transfer Activated by EDREQ Pin Falling Edge...... 372
Figure 8.19 Example of Block Transfer Mode Transfer Activated by EDREQ Pin
Falling Edge......................................................................................................... 373
Figure 8.20 Example of Normal Mode Transfer Activated by EDREQ Pin Low Level......... 374
Figure 8.21 Example of Block Transfer Mode Transfer Activated by EDREQ Pin
Low Level............................................................................................................ 375
Figure 8.22 Example of Single Address Mode (Byte Read) Transfer..................................... 376