Datasheet

Section 7 DMA Controller (DMAC)
Rev. 3.00 Mar 17, 2006 page 309 of 926
REJ09B0283-0300
7.5.8 Basic Bus Cycles
An example of the basic DMAC bus cycle timing is shown in figure 7.17. In this example, word-
size transfer is performed from 16-bit, 2-state access space to 8-bit, 3-state access space. When the
bus is transferred from the CPU to the DMAC, a source address read and destination address write
are performed. The bus is not released in response to another bus request, etc., between these read
and write operations. As like CPU cycles, DMA cycles conform to the bus controller settings.
The address is not output to the external address bus in an access to on-chip memory or an internal
I/O register.
φ
Address bus
DMAC cycle (1-word transfer)
RD
LWR
HWR
Source
address
Destination address
CPU cycle CPU cycle
T
1
T
2
T
3
T
1
T
2
T
3
T
1
T
2
Figure 7.17 Example of DMA Transfer Bus Timing